Motherboards (Intel): Extreme BIOS Glossary

[WiCKeD]

This is a short BIOS guide covering some of the common terms used in current Core i7/Core 2 intel BIOSes.

Some of this will always remain overclocker voodoo, because only the bios programmer has any clue what it actually does and they often use their own terminology. I have no intention of covering everything, but suggesting additions are appreciated.

Overclocking Related

• CPU Ratio Setting: Controls the CPU multiplier
• CPU VCORE: Processor voltage. Increase to add stability to your processor.
• CPU PLL (Phased Lock Loop): Power regulation circuitry voltage. Increase to add stability to the power regulation to your CPU at higher overclocks.
• IOH | NB: Northbridge chipset voltage. Increase to add stability to the Northbridge.
• IOH PCI-E: Northbridge chipset voltage to PCI-E
• ICH | SB: Southbridge chipset voltage. Increase to add stability to the Southbridge.
• ICH PCI-E: Southbridge chipset voltage to PCI-E
• DRAM Bus: Memory voltage. Increase to add stability to your RAM.
• Load-Line Calibration | VCore Droop Control: AKA the infamous "Vdroop," a long-time problem on ASUS boards. Vdroop reduces Vcore fluctuations as the processor load changes, but also reduces stability, requiring a higher idle voltage.
• CPU Special Add: Adds to the CPU Vcore in mV increments. Used for fine adjustments.

Core i7 Specific

• BCLK Frequency: Base clock frequency of your processor. The BCLK frequency x CPU Ratio = your processor speed.
• UCLK: Uncore Clock frequency, which controls the speed of the memory controller and L3 cache. This multi x current BCLK = Uncore Clock frequency.
• QPI Freq | QPI Link Data Rate: QuickPath Interconnect multiplier, which controls the speed between processor and northbridge, similar to AMD's hypertransport multi. This multi x current BCLK = QPI frequency.
• QPI/Dram | CPU VTT: QuickPath Interconnect bus and Uncore voltages. Improves stability of the memory controller and the QPI frequency, to allow higher clocks on the memory and maximium QPI frequency.

Core 2 Specific

• FSB: Motherboard front side bus. The FSB x CPU Ratio: your processor speed.
• CPU GTL voltage reference (0/2): Adjusts the signal frequency where the 0/2 CPU cores operate in response to FSB termination voltage (VTT) changes.
• CPU GTL voltage reference (1/3): Adjusts the signal frequency where the 1/3 CPU cores operate in response to FSB termination voltage (VTT) changes.
• NB GTL Refeference: Adjusts the voltage received in response to VTT changes.
• Clockgen Voltage Control: Increases voltage to reduce noise and stabilize the clock generator at higher frequencies.
• FSB termination Voltage | vFSB | CPU VTT: Provides a grounding voltage that terminates data lines between the NB and CPU and can increase stability.

Processor Related

• Intel HT Technology: Hyperthreading, which allows a core to virtually process two separate threads. Disabling will decrease temps and may allow slightly higher overclocks for improved performance in older, single threaded apps
• Intel VT-d | Intel Vanderpool Virtualization Tech: Allows different software and operating systems to run within other operating systems (ie Linux within Windows)
• Hardware Prefetcher: moves common tasks from main memory into the L2/L3 cache of the processor
• Adjacent Cache Line Prefetch: While processing an instruction set, the processor pulls the next "cache line" into the processor's cache for future processing
• Execute Disable Bit | XD: Processor based security against viruses. If enabled on your processor and in your OS, it prevents the execution of code in system memory assigned to data storage. This can sometimes cause conflicts with legitimate applications. However at high overclocks, Windows versions with DEP enabled (XP SP2+) tend to freak out when this is disabled. I recommend leaving the default and disabling in Windows if you have problems.
• A20M | Gate A20: Used for compatibility to allow 16-bit protected mode in legacy OSes (i.e. Windows 98, DOS and below)
• CPU clock skew: Advances or delays the frequency of the processor by picoseconds in relation to the northbridge, to bring them into alignment at higher overclocks, due to the different electrical trace lengths
• NB Clock Skew | IOH Clock Skew: Advances or delays the frequency of the northbridge by picoseconds in relation to the processor, to bring them into alignment at higher overclocks, due to the different electrical trace lengths
• CPU Spread Spectrum: Shrinks the allowed variance of the wave of the set PCI-E frequency, to reduce EMI. Disabling allows greater variance and may increase overclockability.
• MAX cpuid value limit: "Allows you to circumvent problems with older operating systems" by limiting the maximum CPUID value

Core i7 Specific

• CPU Differential Amplitude: Adjustment to reduce the noise of the frequency wave at higher clocks

Power Related

• EIST (Enhanced Intel Speedstep Technology) | Intel Speedstep Tech: dynamically scales voltage and frequencies at load. Can cause problems while overclocking and reduces max speed
• C1E: dynamically scales voltage and frequencies at idle. Can cause problems while overclocking and reduces max speed
• Intel C-State Tech: sets the processor control state, such as C1E and other idle power states, to dynamically reduce power consumption. Can cause problems while overclocking and reduces max speed
• CPU TM: Controls processor Thermal Management, which throttles your processor to prevent it from overheating. Can cause problems while overclocking and reduces max speed
• ACPI 2.0 Support (Advanced Configuration and Power Interface): Allows an operating system to control the power settings of its peripherals. In order to function, it must be turned on before installing Windows.
• ACPI APIC Support: Enables the Advanced Programmable Interrupt Controller which allows more IRQs for newer operating systems.

Core i7 Specific

• Intel TurboMode: Allows the processor to dynamically increase the speed and power of individual processor core multipliers. For a multi threaded application, it can bump 2 cores by 1x or a single core by 2x. Disabling this may give you an extra multiplier on certain boards.

Memory Related

• Command Rate (CR): Length of time between selecting a different memory chip to address. This has the largest impact on memory performance, but is generally fixed by the motherboard. Set to 1 for the best performance.
• Cas Latency (CL): Number of clock cycles before data is requested out of memory. Reduce for improved performance. In my experience, adjusting this improves performance by <1%.
• RAS to Cas (tRCD): Length of time between memory rows. Reduce for improved performance. In my experience, adjusting this improves performance by <0.5%
• RAS Precharge (tRP): Length of time before a new memory row can be accessed. Reduce for improved performance. In my experience, adjusting this improves performance by about the same as tRP <0.5%
• Cycle Time (tRAS): Length of time a row remains active. Reduce for improved performance. In my experience, this and every memory sub-timing below it have no noticeable effect on performance.
• Dram Clock Skew: Advances/delays the timing in picoseconds between memory slots to the mem controller, due to the different electrical trace lengths
• Dram Command Skew: Advances or delays the frequency at which the first memory chip is addressed.
• DRAM static read control: Improve memory's ability to work at higher frequencies.
• DRAM read training: Improve memory's ability to work at higher frequencies.
• MEM. OC charger: Improve memory's ability to work at higher frequencies.
• AI Clock Twister: "This setting controls the number of memory access phases that are "pulled-in" to the next lower (higher performance) Static Read Delay value."
• More on timings...

Graphics Related

• PCI-E Spread Spectrum: Shrinks the allowed variance of the wave of the set PCI-E frequency, to reduce EMI. Disabling allows greater variance and may increase overclockability.

Below are sample settings to use as a guideline. Your final settings may be very different from these. Voltage settings will change as Intel switches to smaller nanometer processes. Use these at your own risk!

Sample Core i7 (45nm) on Intel X58 chipset Settings:

• CPU Ratio Setting: MANUAL = 21x
• CPU VCORE: MANUAL = 1.43v, SAFE = <1.45v
• CPU PLL (Phased Lock Loop): AUTO = 1.80v
• IOH | NB: AUTO = 1.1v
• IOH PCI-E: AUTO = 1.5v
• ICH | SB: AUTO = 1.05v
• ICH PCI-E: AUTO = 1.5v
• DRAM Bus: MANUAL = 1.65v, SAFE = <1.65v
• Load-Line Calibration: MANUAL = ENABLED
• BCLK Frequency: MANUAL = 200MHz
• UCLK : MANUAL = 3200MHz
• QPI Freq | QPI Link Data Rate: MANUAL = 7218MT/s
• QPI/Dram | CPU VTT: MANUAL = 1.25v
• Intel HT Technology: AUTO = ENABLED
• Intel VT-d | Intel Vanderpool Virtualization Tech: MANUAL = DISABLED
• Hardware Prefetcher: AUTO = ENABLED
• Adjacent Cache Line Prefetch: AUTO = ENABLED
• Execute Disable Bit | XD: AUTO = ENABLED
• A20M | Gate A20: AUTO = DISABLED
• CPU clock skew: AUTO = DEFAULT
• NB Clock Skew | IOH Clock Skew: AUTO = DEFAULT
• CPU Spread Spectrum: MANUAL = DISABLED
• MAX cpuid value limit - AUTO = DISABLED
• CPU Differential Amplitude - AUTO = DEFAULT
• EIST (Enhanced Intel Speedstep Technology) | Intel Speedstep Tech: MANUAL = DISABLED
• C1E: AUTO = ENABLED
• Intel C-State Tech: MANUAL = DISABLED
• CPU TM: MANUAL = DISABLED, SAFE = ENABLED
• ACPI 2.0 Support (Advanced Configuration and Power Interface): AUTO = ENABLED
• ACPI APIC Support: AUTO = ENABLED
• Intel TurboMode: AUTO = ENABLED
• Command Rate (CR): AUTO = 1T
• Cas Latency (CL): MANUAL = 9
• RAS to Cas (tRCD): MANUAL = 9
• RAS Precharge (tRP): MANUAL = 9
• Cycle Time (tRAS): MANUAL = 24
• Dram Clock Skew: AUTO = DEFAULT
• Dram Command Skew: AUTO = DEFAULT
• DRAM static read control: AUTO = DEFAULT
• DRAM read training: AUTO = DEFAULT
• MEM. OC charger: AUTO = DEFAULT
• AI Clock Twister: AUTO = DEFAULT
• PCI-E Spread Spectrum: MANUAL = DISABLED

Sample Core 2 Quad (65nm) on Intel P45 chipset Settings:

• CPU Ratio Setting: MANUAL = 9x
• CPU VCORE: MANUAL = 1.44v, SAFE = <1.45v
• CPU PLL (Phased Lock Loop): AUTO = 1.50v
• Northbridge Voltage : MANUAL = 1.4v
• Southbridge Voltage: AUTO = 1.05v
• DRAM Bus: MANUAL = 2.2v, SAFE = <2.2v
• Vcore Droop Control: MANUAL = DISABLED
• CPU Special Add: AUTO = +0mV
• FSB: MANUAL = 400MHz
• CPU GTL voltage reference (0/2): MANUAL = .67x
• CPU GTL voltage reference (1/3): MANUAL = .67x
• NB GTL Refeference: MANUAL = .63x
• Clockgen Voltage Control: AUTO = 3.45v
• FSB termination Voltage: MANUAL = 1.38v
• Intel HT Technology: AUTO = ENABLED
• Intel VT-d | Intel Vanderpool Virtualization Tech: MANUAL = DISABLED
• Hardware Prefetcher: AUTO = ENABLED
• Adjacent Cache Line Prefetch: AUTO = ENABLED
• Execute Disable Bit | XD: AUTO = ENABLED
• A20M | Gate A20: AUTO = DISABLED
• CPU clock skew: AUTO = DEFAULT
• NB Clock Skew | IOH Clock Skew: AUTO = DEFAULT
• CPU Spread Spectrum: MANUAL = DISABLED
• MAX cpuid value limit: AUTO = DISABLED
• CPU Differential Amplitude: AUTO = DEFAULT
• EIST (Enhanced Intel Speedstep Technology) | Intel Speedstep Tech: AUTO = ENABLED
• C1E: MANUAL = DISABLED
• Intel C-State Tech: MANUAL = DISABLED
• CPU TM: MANUAL = DISABLED, SAFE = ENABLED
• ACPI 2.0 Support (Advanced Configuration and Power Interface): AUTO = ENABLED
• ACPI APIC Support: AUTO = ENABLED
• Intel TurboMode: AUTO = ENABLED
• Command Rate (CR): AUTO = 1T
• Cas Latency (CL): MANUAL = 5
• RAS to Cas (tRCD): MANUAL = 5
• RAS Precharge (tRP): MANUAL = 5
• Cycle Time (tRAS): MANUAL = 15
• Dram Clock Skew: AUTO = DEFAULT
• Dram Command Skew: AUTO = DEFAULT
• DRAM static read control: AUTO = DEFAULT
• DRAM read training: AUTO = DEFAULT
• MEM. OC charger: AUTO = DEFAULT
• AI Clock Twister: AUTO = DEFAULT
• PCI-E Spread Spectrum: MANUAL = DISABLED

Credit goes to TechARP (FKA Adrian's Rojak Pot) for some of these definitions. I highly recommend his Definitive BIOS Guide if you are looking for additional definitions, especially for older boards, although I feel it is missing out on some of the newer definitions. Great guide that has been around for years.

[4-n-zics]

Thanks for this. I recently moved up to an i7 rig and was a little put back by all of the extra stuff in the BIOS. I have not overclocked anything in several years and have never overclocked any intel CPUs.

[WiCKeD]

Glad to help! I figured if everyone was as confused as I was, a guide was badly needed. Many of the "new" i7 settings are really just old terms rebranded and this is causing alot of confusion.

[[GF]Duke]

Great idea putting this up. I'll be moving up to i7 soon so this will def come in handy.

I vote STICKY.

[(\/)agungis]

I have spent the last month looking for this and i can tell you now it was worth it. Thank you!! Sticky it!

[Mr Rat]

In this reply, the very first statement I would like to make is that I am not questioning your understanding of processor architecture nor am I questioning your skills in achieving increased performance of your machine via manipulation of BIOS settings involving voltages, frequencies, timings and the like. I have only experirimented with "overclocking" because I always do reasearch before attempting to change any of the multitude of BIOS settings availalable to me ( my motherboard is an ASUS Rampage II GENE). Unfortunately, it appears that web searches for a specific set of search criteria always result in many DIFFERENT explanations of what I am trying to learn or understand.

With that said, I have happened upon this post on this forum. It seems that I might get some of my many questions answered in ONE place.

Now, to be specific, I am investigating the properties of my Core i7 CPU and am questioning the manipulation of the voltage source to any "PLL" circuit. Being an electrical engineer I have a very good understanding of the term " Phase Locked Loop". It applies to a type of extremely accurate and stable signal ("clock") oscillator. It achieves stability via a feedback loop from it's output to the sampling input of the oscillator as a whole. Once the PLL oscillator is configured to generate a specific frequency, any deviation from that frequency is detected by even the most minute change in "phase" of the output signal (it is impossible for output signal to be EXACTLY the same as the configured frequency if is "out of phase").

Therein lies my question (or argument as it may seem). From a "low level integrated circuitry" point of view, I can see absolutely no benefit whatsoever to changing the supply voltage of any PLL device to something "out of spec" in order to obtain stability for overclocking. In fact, "tweaking" PLL voltages can only have the opposite effect. Any perceived increase in stabilty must be from some other BIOS adjustment that was performed during the same BIOS setup session. I believe I am correct on this point due to the universal nature of "PLL" terminology.

I welcome any feedback and hope to learn a great deal about the art of intelligent overclocking.

[WiCKeD]

Not being an EE, I can only give you my experience and the experience of others on the effect PLL has. You can see in my sample overclock, I left this at default, because it seemed to have no effect on my overclock. However, others have reported additional stability with higher voltages. Raising any voltage in general beyond spec increases the signal strength at the expense of heat and damage from electromigration. There is a balance between the two. Increasing the PLL voltage most likely increases the power regulation circuitry to the clock generator/oscillator to allow it to continue generating a stable frequency. If the voltage is too low, the frequency gets out of spec and the CPU throws errors.

[Mr Rat]

Originally Posted by WiCKeD

Not being an EE, I can only give you my experience and the experience of others on the effect PLL has. You can see in my sample overclock, I left this at default, because it seemed to have no effect on my overclock. However, others have reported additional stability with higher voltages. Raising any voltage in general beyond spec increases the signal strength at the expense of heat and damage from electromigration. There is a balance between the two. Increasing the PLL voltage most likely increases the power regulation circuitry to the clock generator/oscillator to allow it to continue generating a stable frequency. If the voltage is too low, the frequency gets out of spec and the CPU throws errors.

Thanks for your reply.

Due to my technical background I hope I can contribute in a positive way by discussing some terminology used by most overclockers (as I have seen by reading many posts from several overclocking forums as well as the "big guys" like Tom's Hardware and AnandTech) and many misconceptions that overclockers in general appear to have.

First of all I would like to comment on your mention of "signal strength". A "signal", whether sinusoidal, square, rectangular (pulse) or otherwise in and of itself has no strength. If you are thinking in terms of Power (rated in units of Watts) than it is the capaciity of the signal generator itself that determines signal strength. For CPU PLL circuitry there is really no "strenght" to think of. Only frequency stability, accuracy and the ability to maintain an undistorted waveform are of primary concern. Yes, a CPU can consume (and dissipate in the form of heat) over 100 Watts of power but that is distributed throughout if the IC itself and the majority is needed for voltage regulation (DC voltages that is).

That's it for this post except for a question. What do you mean when you say the cpu "throws errors". There is extensive error detection and correction (if possible) occuring at rates in the GHz region but there is no way to see this activity. And, if you could, ther would be so many error events occuring over just a 1 second time interval that you would spend many hours analyzing them.

[WiCKeD]

Errors are detected by running computational programs that typically calculate the value of Pi. If the result is checked against known results and is wrong - the program throws an error and that is the major way overclockers test for stability. This is the method that would be used to test whether increasing the voltage to the PLL increases or decreases stability.

I can see you are interested in the gritty details of it, but I would suggest you look at some of the basic guides on the how overclocking is done and draw on your own experience to determine the why. Maybe you will be able to explain some things to us.

Honestly though, I would say most of us are comfortable with having a cursory idea of how things work and are satisfied by the results that are obtained from repeated trial and error of others' experiences. It may not always be right, but it will eventually get us there.

[WindtalkerCS]

The reason is pretty simple, the PLL is a logic chip just like any other. When overclocking, we are pushing the PLL out of spec along with everything else (assuming you aren't overclocking via the multiplier). Adding more voltage to the device allows it to better define the edges of a clock cycle.

When pushing the clock higher, the edges of the clock tend to become a little more hairy which I'm sure you know. We don't have perfect square waves in computing. When overclocked, those square waves are even less perfect. Adding the voltage allows for a greater noise tolerance, and allows more easily to see that a 1 is indeed a 1 and a 0 is a 0.

[Mr Rat]

Originally Posted by WindtalkerCS

The reason is pretty simple, the PLL is a logic chip just like any other. When overclocking, we are pushing the PLL out of spec along with everything else (assuming you aren't overclocking via the multiplier). Adding more voltage to the device allows it to better define the edges of a clock cycle.

When pushing the clock higher, the edges of the clock tend to become a little more hairy which I'm sure you know. We don't have perfect square waves in computing. When overclocked, those square waves are even less perfect. Adding the voltage allows for a greater noise tolerance, and allows more easily to see that a 1 is indeed a 1 and a 0 is a 0.

Actually, it is no longer that simple as I am learning. I have gone straight to the horses mouth (Intel) and downloaded all the technical literature made available to the public. We are not talking about discrete integrated circuits anymore but a new processor technology which Intel officially refers to as "Quick Path Interconnect". It is a hell of a lot more than an advanced on die memory controller but a new architeture AND a new "protocol" which accomplishes some impressive performance us only a link consisting of just 2 signals. So we're talking high bandwidth SERIAL transactions. The PLL aspect fits in to this also but not in the way I have learned for discrete digital circuitry.

Another thing I learned is that it appears this "BCLK" term was coined by who-knows-who and just caught on. Intel knows nothing about BCLK, base clock or whatever you want to call it. That's because it's not just a square wave or pulse. It is those 2 signals I mentioned which are differential in nature but it goes far beyond that because the new QPI protocol fit into the picture.

I'll post when I "understand" more but there is limited low-level info available because of the proprietary nature of the whole deal.

[WindtalkerCS]

Ok Mr. Rat, you are wayyyyy overthinking this. QPI is a new way of connection, but it has absolutely nothing to do with your original question. I think you need to take a step back and understand how it works at a high level before you start going any deeper because it is quite obvious that you do not.

[Mr Rat]

Originally Posted by WindtalkerCS

Ok Mr. Rat, you are wayyyyy overthinking this. QPI is a new way of connection, but it has absolutely nothing to do with your original question. I think you need to take a step back and understand how it works at a high level before you start going any deeper because it is quite obvious that you do not.

First of all the original post was in reference the way some folks mess with source voltages for PLL circuitry and my statement that this is not a sound practice. Secondly, PLL circuitry is an important part of QPI. I have read many documents by Intel and have learned much and UNDERSTAND more about Core i7 since my first post. I must state that it is YOU sir who does not understand. So you can continue to browse the web and read about recommended BIOS tweaks using terms like "voltage flow" (absurd) and " signal strength" (totally out of context when in reference to a CPU's internal signal generators) and try changing this-and-that until you notice some perceived performance increase, all the time feeling happy as a clam that you are a top notch overclocker.

I will not appologize for these harsh statement because you've got me really...P.O.'ed !

[WindtalkerCS]

Originally Posted by Mr Rat

So you can continue to browse the web and read about recommended BIOS tweaks using terms like "voltage flow" (absurd) and " signal strength" (totally out of context when in reference to a CPU's internal signal generators)

Please show me where anyone said voltage flow, or any such thing. And believe it or not, you don't have to be an electrical engineer (which I am) to understand how these things work.

Secondly signal strength is in no way out of context. Just because you have never heard it in the way that he has used it doesn't mean that it is wrong. The strength and reliability of a square wave is very much a real thing when working with the hardware that we do.

Originally Posted by Mr Rat

and try changing this-and-that until you notice some perceived performance increase, all the time feeling happy as a clam that you are a top notch overclocker

It is not perceived. It is a fact. Raising voltage adds stability. Nobody is saying that adding voltage is increasing the performance, it does however allow you to increase the performance.

In general, it's normally the best course of action to absorb as much information as you can before you start calling out things like this.

[Mr Rat]

Let me tell you about my Dad.

He is 81 years old. He has his favorite chair where he sits to watch TV all the time. I setup a cordles phone and cradle next to his chair so he didn't have to get up when the phone rang. I setup the phone itself so that he has to press the green flash key when he picks it up out of the cradle to answer a call (this was done to prevent the phone from connecting if he accidentilly knocked it out of the cradle). That was over a year ago. I showed him how to answer a phone call when I set it up. I showed him at least 5 other times when he had a problem answering the phone.

He has received hundreds of phone calls since then. Just a while ago the phone rang. I heard him saying "Hello...hello" as the phone continued to ring and ring.

Your replies made me think of him.

[GuitarCrazyo]

how would this be possible to install if u cant get pass the bios password screen... im not sure but taking out the battery to reset the password works for desktops and not laptop...

[cdolphin]

opinion on fixing vDroop for asus boards?
I use load line calibration, but it does seem to cause stability issues

[FX5200]

Originally Posted by GuitarCrazyo

how would this be possible to install if u cant get pass the bios password screen... im not sure but taking out the battery to reset the password works for desktops and not laptop...

It works for desktops AND laptops, but the battery you have to take out on a lappy is usually under the keyboard, NOT the mail battery that powers the laptop.